Technical Field
The present invention relates generally to data communication links. More particularly, the present invention relates to phase detection in a clock-data recovery circuit with decision feedback equalization.
Description of the Background Art
High-speed serial interfaces may be used to communicate data between devices in a system. Such serial interfaces may provide a high data bandwidth across backplanes or between chip devices.
However, challenges and problems are faced due to the high-speed signaling that may be used by these serial interfaces. One challenge relates to obtaining sufficient timing error information for timing recovery in a high-speed transceiver with speculative decision feedback equalization (DFE).